Download Kluwer Reuse Methodology Manual for System on a Chip Designs 3rd Edition

TABLE OF CONTENTS
1. Introduction
    1.1 Goals of This Manual     
    1.2 Design for Reuse: The Challenge         
    1.3 The Emerging Business Model for Reuse
2. The System-on-Chip Design Process
    2.1 A Canonical SoC Design
    2.2 System Design Flow
    2.3 The Specification Problem         
    2.4 The System Design Process
3. System-Level Design Issues: Rules and Tools
    3.1 The Standard Model          
    3.2 Design for Timing Closure: Logic Design Issues        
    3.3 Design for Timing Closure: Physical Design Issues         
    3.4 Design for Verification: Verification Strategy
    3.5 System Interconnect and On-Chip Buses         
    3.6 Design for Bring-Up and Debug: On-Chip Debug Structures
    3.7 Design for Low Power          

    3.8 Design for Test: Manufacturing Test Strategies         

4. The Macro Design Process
    4.1 Overview of IP Design
    4.2 Key Features
    4.3 Planning and Specification          
    4.4 Macro Design and Verification         
    4.5 Soft Macro Productization         
5. RTL Coding Guidelines
    5.1 Overview of the Coding Guidelines
    5.2 Basic Coding Practices       
    5.3 Coding for Portability         
    5.4 Guidelines for Clocks and Resets
    5.5 Coding for Synthesis
    5.6 Partitioning for Synthesis
    5.7 Designing with Memories
    5.8 Code Profiling
6. Macro Synthesis Guidelines
    6.1 Overview of the Synthesis Problem
    6.2 Macro Synthesis Strategy
    6.3 Physical Synthesis
    6.4 RAM and Datapath Generators
    6.5 Coding Guidelines for Synthesis Scripts
7. Macro Verification Guidelines
    7.1 Overview of Macro Verification
    7.2 Inspection as Verification
    7.3 Adversarial Testing
    7.4 Testbench Design
    7.5 Design of Verification Components
    7.6 Getting to 100%
    7.7 Timing Verification
8. Developing Hard Macros
    8.1 Overview
    8.2 Design Issues for Hard Macros
    8.3 The Hard Macro Design Process
    8.4 Productization of Hard Macros
    8.5 Model Development for Hard Macros
    8.6 Porting Hard Macros
9. Macro Deployment: Packaging for Reuse
    9.1 Delivering the Complete Product
    9.2 Contents of the User Guide
10. System Integration with Reusable Macros
      10.1 Integration Overview
      10.2 Integrating Macros into an SoC Design
      10.3 Selecting IP
      10.4 Integrating Memories
      10.5 Physical Design
11. System-Level Verification Issues
      11.1 The Importance of Verification
      11.2 The Verification Strategy

      11.3 Interface Verification
      11.4 Functional Verification
      11.5 Random Testing

      11.6 Application-Based Verification
      11.7 Gate-Level Verification
      11.8 Specialized Hardware for System Verification
12. Data and Project Management
      12.1 Data Management
      12.2 Project Management
13. Implementing Reuse-Based SoC Designs
      13.1 Alcatel 
      13.2 Atmel 
      13.3 Infineon Technologies
      13.4 LSI Logic
      13.5 Philips Semiconductor
      13.6 STMicroelectronics

      13.7 Conclusion

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